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ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
15 years 11 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
IWMM
2010
Springer
211views Hardware» more  IWMM 2010»
15 years 7 months ago
Concurrent, parallel, real-time garbage-collection
With the current developments in CPU implementations, it becomes obvious that ever more parallel multicore systems will be used even in embedded controllers that require real-time...
Fridtjof Siebert
DSN
2005
IEEE
15 years 11 months ago
Fatih: Detecting and Isolating Malicious Routers
Network routers occupy a key role in modern data transport and consequently are attractive targets for attackers. By manipulating, diverting or dropping packets arriving at a comp...
Alper Tugay Mizrak, Yu-Chung Cheng, Keith Marzullo...
ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
15 years 7 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
CONEXT
2007
ACM
15 years 9 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure