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» Design space exploration revisited
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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
14 years 2 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
CORR
2010
Springer
142views Education» more  CORR 2010»
13 years 8 months ago
Budget Feasible Mechanisms
We study a novel class of mechanism design problems in which the outcomes are constrained by the payments. This basic class of mechanism design problems captures many common econom...
Christos H. Papadimitriou, Yaron Singer
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
13 years 8 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar
NOSSDAV
2009
Springer
14 years 4 months ago
Dynamic overlay multicast in 3D video collaborative systems
Multi-stream/multi-site 3D video collaborative systems are promising as they enable remote users to interact in a 3D virtual space with a sense of co-presence. However, the decent...
Wanmin Wu, Zhenyu Yang, Klara Nahrstedt
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 3 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt