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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ISPASS
2008
IEEE
14 years 4 months ago
Configurational Workload Characterization
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect o...
Hashem Hashemi Najaf-abadi, Eric Rotenberg
ISLPED
2010
ACM
184views Hardware» more  ISLPED 2010»
13 years 10 months ago
Hybrid energy storage system integration for vehicles
Energy consumption and the associated environmental impact are a pressing challenge faced by the transportation sector. Emerging electric-drive vehicles have shown promises for su...
Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang
ICCAD
2009
IEEE
131views Hardware» more  ICCAD 2009»
13 years 8 months ago
Scheduling with soft constraints
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
Jason Cong, Bin Liu, Zhiru Zhang
TC
2011
13 years 5 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...