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VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
16 years 5 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
15 years 11 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
CSCW
2010
ACM
16 years 1 months ago
Pictionaire: supporting collaborative design work by integrating physical and digital artifacts
This paper introduces an interactive tabletop system that enhances creative collaboration across physical and digital artifacts. Pictionaire offers capture, retrieval, annotation,...
Björn Hartmann, Meredith Ringel Morris, Hrvoj...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
16 years 5 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
HPCC
2007
Springer
15 years 10 months ago
Towards a Complexity Model for Design and Analysis of PGAS-Based Algorithms
Many new Partitioned Global Address Space (PGAS) programming languages have recently emerged and are becoming ubiquitously available on nearly all modern parallel architectures. PG...
Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazaw...