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CASES
2004
ACM
13 years 11 months ago
Automatic data partitioning for the agere payload plus network processor
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
Steve Carr, Philip H. Sweany
VSTTE
2005
Springer
14 years 1 months ago
From the How to the What
In this paper, we consider the Grand Challenge under a very specific perspective: the enabling of application experts without programming knowledge to reliably model their busines...
Tiziana Margaria, Bernhard Steffen
DAC
2008
ACM
14 years 8 months ago
Parallel programming: can we PLEASE get it right this time?
The computer industry has a problem. As Moore's law marches on, we will be exploiting it to double cores, not frequencies. But all those cores ... 2 to 4 today growing to 8, ...
Tim Mattson, Michael Wrinn
CODES
2006
IEEE
14 years 1 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
VMCAI
2009
Springer
14 years 2 months ago
A Scalable Memory Model for Low-Level Code
Abstract. Because of its critical importance underlying all other software, lowlevel system software is among the most important targets for formal verification. Low-level systems...
Zvonimir Rakamaric, Alan J. Hu