397 search results - page 18 / 80 » Designing Fast Asynchronous Circuits |
ISMVL
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circui...
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
ASYNC
2003
IEEE
14 years 1 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
FPL
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and...
FPGA
1998
ACM
14 years 26 days ago
1998
ACM