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» Designing Fast Asynchronous Circuits
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DATE
2002
IEEE
89views Hardware» more  DATE 2002»
14 years 1 months ago
Generalized Early Evaluation in Self-Timed Circuits
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
Mitchell A. Thornton, Kenneth Fazel, Robert B. Ree...
LICS
1996
IEEE
14 years 25 days ago
Reactive Modules
We present a formal model for concurrent systems. The model represents synchronous and asynchronous components in a uniform framework that supports compositional (assume-guarantee)...
Rajeev Alur, Thomas A. Henzinger
DAC
1999
ACM
14 years 29 days ago
A Practical Approach to Multiple-Class Retiming
Retiming is an optimization technique for synchronous circuits introduced by Leiserson and Saxe in 1983. Although powerful, retiming is not very widely used because it does not ha...
Klaus Eckl, Jean Christophe Madre, Peter Zepter, C...
DAC
2011
ACM
12 years 8 months ago
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials
Stochastic device noise has become a significant challenge for high-precision analog/RF circuits, and it is particularly difficult to correctly include both white noise and flic...
Fang Gong, Hao Yu, Lei He
CASES
2007
ACM
14 years 20 days ago
Performance-driven syntax-directed synthesis of asynchronous processors
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A...