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» Designing Fast Asynchronous Circuits
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VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
14 years 7 months ago
Design of Asynchronous Controllers with Delay Insensitive Interface
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...
Hiroshi Saito, Alex Kondratyev, Takashi Nanya
ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
14 years 4 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
14 years 1 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
ENTCS
2010
113views more  ENTCS 2010»
13 years 7 months ago
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
Dan R. Ghica, Alex Smith
ASPDAC
2001
ACM
127views Hardware» more  ASPDAC 2001»
13 years 11 months ago
High-level design for asynchronous logic
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
Ross Smith, Michiel M. Ligthart