397 search results - page 79 / 80 » Designing Fast Asynchronous Circuits |
ISPD
2007
ACM
13 years 9 months ago
2007
ACM
In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...
DAC
2010
ACM
13 years 7 months ago
2010
ACM
Leveraging the power of nowadays graphics processing units for robust power grid simulation remains a challenging task. Existing preconditioned iterative methods that require inco...
CAL
2007
13 years 7 months ago
2007
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
CPAIOR
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. In recent work binary decision diagrams (BDDs) were introduced as a technique for postoptimality analysis for integer programming. In this paper we show that much smaller...