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» Designing Leakage Aware Multipliers
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GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 10 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
VLSID
2009
IEEE
107views VLSI» more  VLSID 2009»
14 years 7 months ago
Temperature Aware Scheduling for Embedded Processors
Power density has been increasing at an alarming rate in recent processor generations resulting in high on-chip temperature. Higher temperature results in poor reliability and inc...
Ramkumar Jayaseelan, Tulika Mitra
ISLPED
2009
ACM
100views Hardware» more  ISLPED 2009»
14 years 1 months ago
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Post-fabrication tuning for mitigating manufacturing variability is receiving a significant attention. To reduce leakage increase involved in performance compensation by body bia...
Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuya...
DSD
2009
IEEE
84views Hardware» more  DSD 2009»
14 years 1 months ago
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
— 3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates tempe...
Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simu...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 21 days ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...