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» Designing Leakage Aware Multipliers
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ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
13 years 12 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
TVLSI
2010
13 years 1 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
ISQED
2009
IEEE
91views Hardware» more  ISQED 2009»
14 years 1 months ago
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
DAC
2009
ACM
14 years 7 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...
DATE
2007
IEEE
148views Hardware» more  DATE 2007»
14 years 1 months ago
Temperature aware task scheduling in MPSoCs
In deep submicron circuits, elevation in temperatures has brought new challenges in reliability, timing, performance, cooling costs and leakage power. Conventional thermal managem...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...