Sciweavers

2945 search results - page 103 / 589
» Designing and Implementing Malicious Hardware
Sort
View
FPL
2000
Springer
103views Hardware» more  FPL 2000»
15 years 8 months ago
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem
Many applications can be modeled as subgraph isomorphism problems. However, this problem is generally NP-complete and difficult to compute. A custom computing circuit is a prospect...
Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangth...
ISMVL
1998
IEEE
105views Hardware» more  ISMVL 1998»
15 years 8 months ago
A Review of Multiple-Valued Memory Technology
This paper provides a brief overview of semiconductor memory design from the perspective of the impact multiplevalued circuit techniques are making on modern day implementations. ...
P. Glenn Gulak
MSO
2003
15 years 5 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
DSD
2010
IEEE
133views Hardware» more  DSD 2010»
15 years 1 months ago
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
Igor Lemberski, Petr Fiser
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
15 years 9 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick