2945 search results - page 35 / 589 » Designing and Implementing Malicious Hardware |
122
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ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
— In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/I...
ISCAS
2007
IEEE
15 years 10 months ago
2007
IEEE
— We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing in...
135
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FSE
2004
Springer
15 years 7 months ago
2004
Springer
Abstract. We present a fast involutional block cipher optimized for reconfigurable hardware implementations. ICEBERG uses 64-bit text blocks and 128-bit keys. All components are in...
154
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ISSS
2002
IEEE
15 years 9 months ago
2002
IEEE
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
146
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FCCM
2006
IEEE
15 years 10 months ago
2006
IEEE
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...