2945 search results - page 467 / 589 » Designing and Implementing Malicious Hardware |
157
Voted
MICRO
2002
IEEE
15 years 5 months ago
2002
IEEE
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
183
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CCR
2011
15 years 1 months ago
2011
Proliferation and innovation of wireless technologies require significant amounts of radio spectrum. Recent policy reforms by the FCC are paving the way by freeing up spectrum fo...
229
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TVLSI
2010
15 years 26 days ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
194
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CF
2009
ACM
16 years 21 days ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
180
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CODES
2007
IEEE
16 years 15 days ago
2007
IEEE
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...