Sciweavers

2945 search results - page 59 / 589
» Designing and Implementing Malicious Hardware
Sort
View
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
16 years 1 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
149
Voted
SIGIR
2003
ACM
15 years 9 months ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder
IPPS
1999
IEEE
15 years 8 months ago
Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer
This paper describes a dynamically reconfigurable hardware-based computer called the Plastic Cell Architecture (PCA). PCA consists of dualstructured sea-of -cells that consist of a...
Hiroshi Nakada, Kiyoshi Oguri, Norbert Imlig, Mino...
AADEBUG
2005
Springer
15 years 9 months ago
An integrated debugging environment for reprogrammble hardware systems
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...
Kevin Camera, Hayden Kwok-Hay So, Robert W. Broder...
FPL
2004
Springer
106views Hardware» more  FPL 2004»
15 years 9 months ago
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
Leandro Möller, Ney Laert Vilar Calazans, Fer...