2945 search results - page 68 / 589 » Designing and Implementing Malicious Hardware |
117
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper we discuss two ways to provide flexible hardware support for the reduction step in Elliptic Curve Cryptography in binary fields (GF(2m )). In our first approach w...
137
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FPL
2008
Springer
15 years 5 months ago
2008
Springer
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
146
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ASPLOS
2011
ACM
14 years 7 months ago
2011
ACM
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
147
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CHES
2009
Springer
16 years 4 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
189
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VLSID
1999
IEEE
15 years 8 months ago
1999
IEEE
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...