114 search results - page 17 / 23 » Designing for Xilinx XC6200 FPGAs |
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
VLSISP
2011
13 years 2 months ago
2011
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
ASPDAC
2012
ACM
12 years 3 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...