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DATE
2006
IEEE
121views Hardware» more  DATE 2006»
15 years 10 months ago
Analysis of the impact of bus implemented EDCs on on-chip SSN
In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN...
Daniele Rossi, Carlo Steiner, Cecilia Metra
DSN
2006
IEEE
15 years 10 months ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 10 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
LCPC
2005
Springer
15 years 10 months ago
Concurrency Analysis for Parallel Programs with Textually Aligned Barriers
Abstract. A fundamental problem in the analysis of parallel programs is to determine when two statements in a program may run concurrently. This analysis is the parallel analog to ...
Amir Kamil, Katherine A. Yelick
ICCBSS
2003
Springer
15 years 9 months ago
Protective Wrapper Development: A Case Study
We have recently proposed a general approach to engineering protective wrappers as a means of detecting errors or unwanted behaviour in systems employing an OTS (Off-The-Shelf) ite...
Tom Anderson, Mei Feng, Steve Riddle, Alexander B....