— In this paper, we introduce a novel Markov Chain (MC) representation aided Minimum Bit Error Rate (MBER) detection method that is applicable to an M-QAM modulated SDM/SDMA upli...
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Because of the rapidly shrinking dimensions in VLSI, transient and permanent faults arise and will continue to occur in the near future in increasing numbers. Since cryptographic c...