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PACS
2000
Springer
121views Hardware» more  PACS 2000»
13 years 11 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
RTAS
2003
IEEE
14 years 24 days ago
An Integrated Approach for Applying Dynamic Voltage Scaling to Hard Real-Time Systems
Wireless and portable devices depend on the limited power supplied by the battery. Dynamic Voltage Scaling (DVS) is an effective method to reduce CPU power consumption. For real-t...
Yanbin Liu, Aloysius K. Mok
DAC
2001
ACM
14 years 8 months ago
Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors
Energy consumption has become an increasingly important consideration in designing many real-time embedded systems. Variable voltage processors, if used properly, can dramatically...
Gang Quan, Xiaobo Hu
ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
13 years 5 months ago
Mitigation of intra-array SRAM variability using adaptive voltage architecture
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
Ashish Kumar Singh, Ku He, Constantine Caramanis, ...
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 8 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan