9 search results - page 2 / 2 » Deterministic BIST with multiple scan chains |
DATE
2002
IEEE
14 years 14 days ago
2002
IEEE
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
DFT
2005
IEEE
13 years 9 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
GLVLSI
2003
IEEE
14 years 24 days ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
ITC
2003
IEEE
14 years 23 days ago
2003
IEEE
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...