60 search results - page 7 / 12 » Deterministic Clock Gating for Microprocessor Power Reductio... |
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
GLVLSI
2003
IEEE
14 years 26 days ago
2003
IEEE
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
CF
2005
ACM
13 years 9 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...