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» Deterministic Restrictions in Circuit Complexity
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IPPS
2003
IEEE
14 years 19 days ago
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
Daniel Wiklund, Dake Liu
DAC
2002
ACM
14 years 8 months ago
A solenoidal basis method for efficient inductance extraction
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
Hemant Mahawar, Vivek Sarin, Weiping Shi
VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 7 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
FOCS
1999
IEEE
13 years 11 months ago
Near-Optimal Conversion of Hardness into Pseudo-Randomness
Various efforts ([?, ?, ?]) have been made in recent years to derandomize probabilistic algorithms using the complexity theoretic assumption that there exists a problem in E = dti...
Russell Impagliazzo, Ronen Shaltiel, Avi Wigderson
JCSS
2000
116views more  JCSS 2000»
13 years 7 months ago
Time-Space Tradeoffs for Satisfiability
We give the first nontrivial model-independent time-space tradeoffs for satisfiability. Namely, we show that SAT cannot be solved simultaneously in n1+o(1) time and n1space for an...
Lance Fortnow