With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Various efforts ([?, ?, ?]) have been made in recent years to derandomize probabilistic algorithms using the complexity theoretic assumption that there exists a problem in E = dti...
Russell Impagliazzo, Ronen Shaltiel, Avi Wigderson
We give the first nontrivial model-independent time-space tradeoffs for satisfiability. Namely, we show that SAT cannot be solved simultaneously in n1+o(1) time and n1space for an...