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ATS
1995
IEEE
91views Hardware» more  ATS 1995»
14 years 2 months ago
Deterministic test generation for non-classical faults on the gate level
Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck
ET
2010
122views more  ET 2010»
13 years 8 months ago
Fault Models for Quantum Mechanical Switching Networks
This work justifies several quantum gate level fault models and discusses the causal error mechanisms thwarting correct function. A quantum adaptation of the classical test set gen...
Jacob D. Biamonte, Jeff S. Allen, Marek A. Perkows...
ITC
1993
IEEE
148views Hardware» more  ITC 1993»
14 years 3 months ago
DELTEST: Deterministic Test Generation for Gate-Delay Faults
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
Udo Mahlstedt
DATE
1998
IEEE
92views Hardware» more  DATE 1998»
14 years 3 months ago
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis...
ISMVL
2005
IEEE
90views Hardware» more  ISMVL 2005»
14 years 4 months ago
Test Generation and Fault Localization for Quantum Circuits
It is believed that quantum computing will begin to have a practical impact in industry around year 2010. We propose an approach to test generation and fault localization for a wi...
Marek A. Perkowski, Jacob Biamonte, Martin Lukac