Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques

A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach.

• Type: Conference
• Year: 1998
• Where: DATE
• Authors: Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
• Keywords: DATE 1998, Gate Level, Hardware, Sequential Circuit Test, Test Enhancement Techniques