289 search results - page 33 / 58 » Developing Parallel Architectures for Range and Image Sensor... |
111
Voted
ISCA
2005
IEEE
15 years 9 months ago
2005
IEEE
Performance asymmetry in multicore architectures arises when individual cores have different performance. Building such multicore processors is desirable because many simple cores...
136
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GLVLSI
2007
IEEE
15 years 10 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
125
Voted
ISCA
1997
IEEE
15 years 8 months ago
1997
IEEE
This work provides a systematic study of the impact of communication performance on parallelapplications in a high performance network of workstations. We develop an experimental ...
138
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DAC
2002
ACM
16 years 5 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
144
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IEEEPACT
2009
IEEE
15 years 1 months ago
2009
IEEE
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...