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» Developing a Hardware Evaluation Method for SHA-3 Candidates
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DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 2 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin
ECBS
2010
IEEE
147views Hardware» more  ECBS 2010»
14 years 1 months ago
Supporting Customizable Architectural Design Decision Management
—When engineering complex software systems, the key Architectural Design Decisions (ADD) and the reasoning underlying those decisions need to be fully understood by all stakehold...
Lianping Chen, Muhammad Ali Babar
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 1 months ago
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
ICCD
2004
IEEE
137views Hardware» more  ICCD 2004»
14 years 5 months ago
Comparative Study of Strategies for Formal Verification of High-Level Processors
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
Miroslav N. Velev
ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
14 years 4 days ago
Vector instruction set support for conditional operations
Vector instruction sets are receiving renewed interest because of their applicability to multimedia. Current multimedia instruction sets use short vectors with SIMD implementation...
James E. Smith, Greg Faanes, Rabin A. Sugumar