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CODES
2007
IEEE
15 years 8 months ago
Influence of procedure cloning on WCET prediction
For the worst-case execution time (WCET) analysis, especially loops are an inherent source of unpredictability and loss of precision. This is caused by the difficulty to obtain sa...
Paul Lokuciejewski, Heiko Falk, Martin Schwarzer, ...
CODES
2009
IEEE
15 years 8 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
149
Voted
CODES
2004
IEEE
15 years 8 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
176
Voted
CODES
2004
IEEE
15 years 8 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
CBMS
2006
IEEE
15 years 8 months ago
A Distributed Workflow Management System for Automated Medical Image Analysis and Logistics
Advances in medical image analysis have increased the need to integrate and deploy image analysis software in daily clinical routine and in epidemiological studies. We developed a...
Jeroen G. Snel, Sílvia Delgado Olabarriaga,...
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