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MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
14 years 2 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
FOCS
2007
IEEE
14 years 2 months ago
On the Complexity of Nash Equilibria and Other Fixed Points (Extended Abstract)
d Abstract) Kousha Etessami LFCS, School of Informatics University of Edinburgh Mihalis Yannakakis Department of Computer Science Columbia University We reexamine what it means to...
Kousha Etessami, Mihalis Yannakakis
ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 4 months ago
A theory of Error-Rate Testing
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
Shideh Shahidi, Sandeep Gupta
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 2 months ago
Automatic synthesis of compressor trees: reevaluating large counters
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
Ajay K. Verma, Paolo Ienne
CASES
2007
ACM
13 years 11 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...