787 search results - page 126 / 158 » Digital Algebra and Circuits |
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
– Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
DAC
2003
ACM
14 years 27 days ago
2003
ACM
Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targe...
PADS
2003
ACM
14 years 26 days ago
2003
ACM
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...