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ISLPED
2010
ACM
183views Hardware» more  ISLPED 2010»
13 years 7 months ago
A pareto-algebraic framework for signal power optimization in global routing
This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is mini...
Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan ...
ICCD
2005
IEEE
221views Hardware» more  ICCD 2005»
14 years 4 months ago
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
Abstract— Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC ...
Brock J. LaMeres, Sunil P. Khatri
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 24 days ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
DAC
2010
ACM
13 years 11 months ago
Scalable specification mining for verification and diagnosis
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
Wenchao Li, Alessandro Forin, Sanjit A. Seshia
IPSN
2010
Springer
13 years 9 months ago
Hibernets: energy-efficient sensor networks using analog signal processing
In-network processing is recommended for many sensor network applications to reduce communication and improve energy efficiency. However, constraints on memory, speed, and energy ...
Brandon Rumberg, David W. Graham, Vinod Kulathuman...