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ISPD
2005
ACM
140views Hardware» more  ISPD 2005»
14 years 2 months ago
Are floorplan representations important in digital design?
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 2 months ago
Macromodeling of Digital I/O Ports for System EMC Assessment
This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A ...
Igor S. Stievano, Flavio G. Canavero, Ivan A. Maio...
TVLSI
2011
343views more  TVLSI 2011»
13 years 4 months ago
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression
—A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional ...
Shih-Yuan Kao, Shen-Iuan Liu
SPAA
2004
ACM
14 years 2 months ago
Lower bounds for graph embeddings and combinatorial preconditioners
Given a general graph G, a fundamental problem is to find a spanning tree H that best approximates G by some measure. Often this measure is some combination of the congestion and...
Gary L. Miller, Peter C. Richter
ISPD
2007
ACM
124views Hardware» more  ISPD 2007»
13 years 10 months ago
Accurate power grid analysis with behavioral transistor network modeling
In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...
Anand Ramalingam, Giri Devarayanadurg, David Z. Pa...