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» Dimensions in program synthesis
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IIE
2007
125views more  IIE 2007»
13 years 9 months ago
Should LOGO Keep Going FORWARD 1?
LOGO has been evolving in incremental steps for 40 years. This has resulted in steady progress but some regions of the space of all programming languages for children cannot be re...
Ken Kahn
PPOPP
2012
ACM
12 years 5 months ago
PARRAY: a unifying array representation for heterogeneous parallelism
This paper introduces a programming interface called PARRAY (or Parallelizing ARRAYs) that supports system-level succinct programming for heterogeneous parallel systems like GPU c...
Yifeng Chen, Xiang Cui, Hong Mei
DAC
2004
ACM
14 years 11 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
14 years 4 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...
DATE
2007
IEEE
130views Hardware» more  DATE 2007»
14 years 4 months ago
Development of on board, highly flexible, Galileo signal generator ASIC
Alcatel Alenia Space is deeply involved in the Galileo program at many stages. In particular, Alcatel Alenia Space has successfully designed and delivered the very first navigatio...
Louis Baguena, Emmanuel Liégeon, Alexandra ...