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CODES
2008
IEEE
14 years 2 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
14 years 2 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
CHES
2007
Springer
327views Cryptology» more  CHES 2007»
14 years 2 months ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima
NOMS
2006
IEEE
105views Communications» more  NOMS 2006»
14 years 2 months ago
Adaptive Flow Aggregation - A New Solution for Robust Flow Monitoring under Security Attacks
— Flow-level traffic measurement is required for a wide range of applications including accounting, network planning and security management. A key design challenge is how to gr...
Yan Hu, Dah-Ming Chiu, John C. S. Lui
CASES
2003
ACM
14 years 1 months ago
A low-power accelerator for the SPHINX 3 speech recognition system
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous natur...
Binu K. Mathew, Al Davis, Zhen Fang