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» Distributing the Frontend for Temperature Reduction
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GLVLSI
2010
IEEE
136views VLSI» more  GLVLSI 2010»
14 years 24 days ago
Thermal-aware compilation for system-on-chip processing architectures
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...
Mohamed M. Sabry, José L. Ayala, David Atie...
ICS
2000
Tsinghua U.
13 years 11 months ago
Compiling object-oriented data intensive applications
Processing and analyzing large volumes of data plays an increasingly important role in many domains of scienti c research. High-level language and compiler support for developing ...
Renato Ferreira, Gagan Agrawal, Joel H. Saltz
ECCV
2008
Springer
14 years 6 months ago
Window Annealing over Square Lattice Markov Random Field
Monte Carlo methods and their subsequent simulated annealing are able to minimize general energy functions. However, the slow convergence of simulated annealing compared with more ...
Ho Yub Jung, Kyoung Mu Lee, Sang Uk Lee
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
13 years 11 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
DAC
2000
ACM
14 years 8 months ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...