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» Domain Reduction for the Circuit Constraint
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DAC
2006
ACM
14 years 8 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
13 years 11 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
STOC
2009
ACM
160views Algorithms» more  STOC 2009»
14 years 8 months ago
CSP gaps and reductions in the lasserre hierarchy
We study integrality gaps for SDP relaxations of constraint satisfaction problems, in the hierarchy of SDPs defined by Lasserre. Schoenebeck [25] recently showed the first integra...
Madhur Tulsiani
TCAD
2008
172views more  TCAD 2008»
13 years 7 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
CONSTRAINTS
2011
13 years 2 months ago
A global constraint for total weighted completion time for unary resources
We introduce a novel global constraint for the total weighted completion time of activities on a single unary capacity resource. For propagating the constraint, we propose an O(n4...
András Kovács, J. Christopher Beck