173 search results - page 20 / 35 » Domain Reduction for the Circuit Constraint |
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
VLSI
2007
Springer
14 years 1 months ago
2007
Springer
— While physically driven synthesis techniques have proven to be an effective method to meet tight timing constraints required by a design, the incremental placement step during ...
DFT
2003
IEEE
14 years 20 days ago
2003
IEEE
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, we obtain the lower bounds on total energy dissipation of deep submicron (DSM) VLSI circuits via an informationtheoretic framework. This framework enables the deriv...