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» Domain Reduction for the Circuit Constraint
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ISPD
2006
ACM
84views Hardware» more  ISPD 2006»
14 years 1 months ago
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...
Mongkol Ekpanyapong, Sung Kyu Lim
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 9 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
DAC
2004
ACM
14 years 8 months ago
An approach to placement-coupled logic replication
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
Milos Hrkic, John Lillis, Giancarlo Beraudo
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 4 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
DAC
2009
ACM
14 years 8 months ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...