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» Dynamic Functional Unit Assignment for Low Power
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HPCA
2005
IEEE
14 years 7 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
CASES
2004
ACM
14 years 15 days ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker
ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 4 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
HICSS
2008
IEEE
94views Biometrics» more  HICSS 2008»
14 years 1 months ago
Reference Values for Dynamic Calibration of PMUs
1 This paper discusses measurements of the dynamic performance of electric power Phasor Measurement Units, PMUs, and their relation to the requirements of the IEEE Synchrophasor St...
Gerard Stenbakken, Tom Nelson, Ming Zhou, Virgilio...
DATE
2005
IEEE
140views Hardware» more  DATE 2005»
14 years 21 days ago
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Mar...