473 search results - page 18 / 95 » Dynamic Memory Design for Low Data-Retention Power |
VLSID
2006
IEEE
14 years 9 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
CODES
2004
IEEE
14 years 12 days ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
The market demand for portable multimedia applications has exploded in the recent years. Unfortunately, for such applications current compilers and software optimization methods o...
ISLPED
2006
ACM
14 years 2 months ago
2006
ACM
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
CODES
2011
IEEE
12 years 8 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...