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» Dynamic Memory Design for Low Data-Retention Power
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ANCS
2009
ACM
13 years 6 months ago
Progressive hashing for packet processing using set associative memory
As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing e...
Michel Hanna, Socrates Demetriades, Sangyeun Cho, ...
VLSID
2004
IEEE
85views VLSI» more  VLSID 2004»
14 years 9 months ago
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM ch...
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Drape...
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
14 years 1 months ago
Power minimization using system-level partitioning of applications with quality of service requirements
Design systems to provide various quality of service (QoS) guarantees has received a lot of attentions due to the increasing popularity of real-time multimedia and wireless commun...
Gang Qu, Miodrag Potkonjak
ISCAS
2002
IEEE
88views Hardware» more  ISCAS 2002»
14 years 1 months ago
Low depth carry lookahead addition using charge recycling threshold logic
The main result of this paper is the development of a low depth carry lookahead addition technique based on threshold logic. Two such adders are designed using the recently propos...
Peter Celinski, Said F. Al-Sarawi, Derek Abbott, J...
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
14 years 2 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...