473 search results - page 35 / 95 » Dynamic Memory Design for Low Data-Retention Power |
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
DAC
2011
ACM
12 years 8 months ago
2011
ACM
The deployment of computer vision algorithms in mobile applications is growing at a rapid pace. A primary component of the computer vision software pipeline is feature extraction,...
ISCAS
2002
IEEE
14 years 1 months ago
2002
IEEE
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...
VLSID
2009
IEEE
14 years 9 months ago
2009
IEEE
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
TVLSI
2008
13 years 8 months ago
2008
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...