1815 search results - page 12 / 363 » Dynamic Power Management Using Data Buffers |
ICDCS
2006
IEEE
14 years 1 months ago
2006
IEEE
In a distributed environment the utilization of file buffer caches in different clients may vary greatly. Cooperative caching is used to increase cache utilization by coordinatin...
ISSS
1999
IEEE
14 years 5 days ago
1999
IEEE
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
CASES
2007
ACM
13 years 12 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...