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» Dynamic Voltage and Cache Reconfiguration for Low Power
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HPCA
2005
IEEE
14 years 29 days ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
DAC
2008
ACM
14 years 8 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
ICETET
2009
IEEE
13 years 5 months ago
High Performance WDM Using Semiconductor Tunable Laser
Advances in optical networking have lead to the explosive growth of communication network. Telecom applications began to drive significant investments into this field to support t...
S. S. Agrawal, K. D. Kulat, M. B. Daigavane
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
13 years 11 months ago
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar proces
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
14 years 2 months ago
An efficent dynamic multicast routing protocol for distributing traffic in NOCs
Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock sync...
Masoumeh Ebrahimi, Masoud Daneshtalab, Mohammad Ho...