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» Dynamic overlay of scratchpad memory for energy minimization
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HPCA
2002
IEEE
14 years 10 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
WISES
2003
13 years 11 months ago
Locating Moving Objects over Mobile Sensor Network
The purpose of our on going research would be to track entities, which enter their field of vision over the sensor network. Based on their sightings, they maintain a dynamic cache ...
Arvind Nath Rapaka, Sandeep Bogollu, Donald C. Wun...
SBACPAD
2004
IEEE
86views Hardware» more  SBACPAD 2004»
13 years 11 months ago
Multi-Profile Instruction Based Compression
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
14 years 5 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
DAC
1997
ACM
14 years 2 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...