3 search results - page 1 / 1 » Dynamic single-rail self-timed logic structures for power ef... |
GLVLSI
2003
IEEE
14 years 4 months ago
2003
IEEE
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
ISCA
2005
IEEE
14 years 4 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
ISCA
2011
IEEE
13 years 2 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...