Sciweavers

107 search results - page 12 / 22
» Dynamic voltage and frequency scaling circuits with two supp...
Sort
View
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 10 hour ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
14 years 22 days ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
DAC
1999
ACM
13 years 11 months ago
Multi-Time Simulation of Voltage-Controlled Oscillators
We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency mo...
Onuttom Narayan, Jaijeet S. Roychowdhury
ICPPW
2007
IEEE
14 years 1 months ago
Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
Gang Qu
DAC
1997
ACM
13 years 11 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...