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DAC
2005
ACM
14 years 7 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
14 years 7 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
13 years 10 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...
ICCD
2007
IEEE
98views Hardware» more  ICCD 2007»
14 years 3 months ago
Priority-monotonic energy management for real-time systems with reliability requirements
Considering the impact of the popular energy management technique Dynamic Voltage and Frequency Scaling (DVFS) on system reliability, the Reliability-Aware Power Management (RA-PM...
Dakai Zhu, Xuan Qi, Hakan Aydin
DATE
2002
IEEE
100views Hardware» more  DATE 2002»
13 years 11 months ago
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose