130 search results - page 6 / 26 » Dynamically Scheduling VLIW Instructions |
LCTRTS
2001
Springer
13 years 12 months ago
2001
Springer
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In this work, we experiment with complier-directed instruction duplication to detect soft errors in VLIW datapaths . In the proposed approach, the compiler determines the instruct...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
MICRO
1993
IEEE
13 years 11 months ago
1993
IEEE
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...