Sciweavers

27 search results - page 5 / 6
» EEMBC and the Purposes of Embedded Processor Benchmarking
Sort
View
CODES
2003
IEEE
14 years 22 days ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
CASES
2005
ACM
13 years 9 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
CASES
2007
ACM
13 years 9 months ago
Facilitating compiler optimizations through the dynamic mapping of alternate register structures
Aggressive compiler optimizations such as software pipelining and loop invariant code motion can significantly improve application performance, but these transformations often re...
Chris Zimmer, Stephen Roderick Hines, Prasad Kulka...
DAC
2004
ACM
14 years 8 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
CODES
2007
IEEE
14 years 1 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid